Performance assessment of symmetric double gate negative capacitance junctionless transistor with high-k spacer at elevated temperatures

Hema Mehta and Harsupreet Kaur

  • ANSN Editor
Keywords: nano


The present work focuses on investigating the performance of short channel symmetric Double Gate Negative Capacitance Junctionless Transistor (DGNCJLT) with high-k spacers at elevated temperatures. The device behaviour has been explored for a temperature range of 300–380 K by obtaining self consistent solution based on standard Poisson's equation, current continuity equation and Landau-Khalatnikov equation. The impact of high-k spacer lengths and dielectric constants has been explored on device behaviour at high temperature. Also, to alleviate the degradation in device behaviour at high temperature and to achieve sub-60 mV/dec operation even at elevated temperatures, optimisation of ferroelectric layer parameters has been done. It has been demonstrated that by optimising various parameters such as ferroelectric layer thickness, coercive field and remanent polarisation, device performance can be improved significantly even at high temperatures.
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